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x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r d ecember 2010 rev. 1.1. 1 exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668 - 70 00 C fax. +1 510 668 - 70 01 general description the xrp 7713 is a three output pulse - width modulated (pwm) step - down dc - dc controller with a built - in ldo for standby power and gpios. the device provides a complete power management solution in one ic and is fully programmable via an i 2 c serial interface. independent digital pulse width modulator (dpwm) channels regulate output voltages and provide all required protection functions such as current limiti ng and over - voltage protection. each output voltage can be programmed from 0.9v to 5 .1v without the need of an external voltage divider. the wide range of the programmable dpwm switching frequency (from 300 khz to 1.5 mhz) enables the user to optimize between efficiency and component size. input voltage range is from 4.75 v to 2 5 v. an i 2 c bus interface is provided to program the ic as well as to communicate with the host for fault reporting and handling, power rail parameters monitoring, etc. the device offers a complete solution including independently programmable: soft - start, soft - stop, start - up delay and ramp of each pwm regulator. applications ? multi channel power supplies ? audio - video equipments ? industrial & telecom equipments ? processors & dsps based equipments features ? 3 channel step down controller ? programmable output voltage 0.9v - 5. 1v ? programmable 1.5mhz dpwm frequency ? integrated fet drivers ? 4.75 v to 5.5v and 5.5v to 25 v input voltage range ? up to 5 r econfigurable gpio p ins ? fully p rogrammable via i 2 c i nterface ? independent digital pulse width modulator (dpwm) channels ? complete m onitoring and r eporting ? complete power up/down sequencing ? full on board protection otp, uvlo, ocp and ovp ? built - in 3.3v/5v ldo ? powerarchitect? design software ? green/halogen free 32 - pin tqfn typical application diagram fig. 1 : xrp 7713 application diagram
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 2 / 29 rev. 1.1. 1 absolute maximum rat ings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. vcca, vccd, ldoout, glx, voutx ............................ 6v vdd ..................................................................... 2.0v vin ....................................................................... 2 7 v lxx .............................................................. - 1v to 2 7 v lxx ............................................................. - 5v to - 1v 1 logic inputs , gpios, sda, scl ................................... 6v bstx, ghx .................................................... v lxx + 6 v esd rating (hbm - human body model) .................... 2kv storage temperature .............................. - 65c to 150c lead temperature (soldering, 10 sec) ................... 300c operating ratings input voltage range ..................................... 5. 5 v to 25v input voltage vin=vcca ........................... 4.75v to 5.5v junction temperature range .................... - 40c to 1 25c thermal resistance ja ...................................... 2 2 c/w note 1 : 200ns transient electrical specifica tions specifications with standard type are for an operating junction temperature of t j = 25c only; limits applying over the full operating junction temperature ra nge are denoted by a ? . minimum and maximum limits are guaranteed through test, design, or statistical correlation. typical values represent the most likely parametric norm at t j = 25c, and are provided for reference purposes only. unless otherwise indi cated, v in = 4 . 7 5 v to 2 5 v . quiescent current parameter min. typ. max. units conditions vin supply current in standby 9 ma ldoout enabled (no load) no switching converter channels enabled i 2 c communication active switching frequency = 400khz vin supply current in shutdown 180 a en=0v, vin 5.2v vin supply current 28 ma 3 channels running, gh and gh = 1nf load each vin=12v, switching frequency = 300khz vin supply current 50 ma 3 channels running, gh and gh = 1nf load each vin=12v, switching frequency = 1mhz step down controllers parameter min. typ. max. units conditions vout regulation accuracy - 20 20 mv ? 0.9 v vout 2.5v - 40 40 mv ? 2.6v vout 5.1v vout regulation range 0.9 5.1 ? programmable range of each channel 2 vout set point resolution 50 0.9 v vout 2.5v vout set point resolution 100 2.6 v vout 5.1v vout input current 100 na 0.9 v < vout <= 2.5v vout input resistance 120 k ? 2.6 v vout 5.1v note 2 : voltages above 5.1v can be obtained by using an external voltage divider.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 3 / 29 rev. 1.1. 1 low drop - out regulator parameter min. typ. max. units conditions ldoout output voltage ldo=low 3.15 3.3 3.45 v ? 4.75 v vin2 5 v 0ma x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 4 / 29 rev. 1.1. 1 digita l input/output pins (gpio1 - gpio5 ) and enable 3.3v cmos logic compatible, 5v tolerant . parameter min. typ. max. units conditions enable pin threshold 1.08 1.14 1.2 v chip enable rising threshold input pin low level 0. 8 v ? input pin high level 2. 0 v ? input pin leakage current 1 0 a ? v io =3.3v input pin capacitance 5 pf output pin low level 0. 4 v ? i sink = 1 ma output pin high level 2.4 v ? i source =1ma output pin high level (no load) 3.3 3.6 v ? i source =0ma i 2 c specification parameter min. typ. max. units conditions i 2 c speed 400 khz based upon i 2 c master clock input pin low level, v il 1.0 v input pin high level, v i h 2. 31 v hysteresis of schmitt trigger inputs, v hys 0.165 v output pin low level (open drain or collector) v ol 0.4 v i sink =3ma input leakage current - 10 10 a input is between 0.33v and 2.31 v output fall time from v ihmin to v ilmax 20+0.1c b 3 250 ns with a bus capacitance from 10pf to 400pf capacitance for each i/o pin 10 pf note 3 : c b is the capacitance o f one bus in pf gate drivers parameter min. typ. max. units conditions gh, gl rise and fall time 30 ns at 10% to 90% of full scale pulse. 1nf c load gh, gl pull - up on - state output resistance 6 ? gh, gl pull - down on - state output resistance 3 ? gh, gl pull - down off - state output resistance 50 k ? vin=vccd=0v
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 5 / 29 rev. 1.1. 1 block diagram bst1 gpio 0-3 channel 1 C 6 gh1 gl1 lx1 pgnd1 vin vcc vdd ldoout hybrid dpwm digital pid feedback adc1/2 vtar dac prescaler ss & pd delay gate driver vout1 bst2 channel 2 gh2 gl2 lx2 pgnd2 hybrid dpwm digital pid feedback adc1/2 vtar dac prescaler ss & pd dead time gate driver vccd vout2 channel 3 ldo 11-ch mux current adc1/2 vout1 vout2 vout3 vtj stby lr gpio i2c sda,scl otp vref osc clock pwr good configuration registers vout3 uvlo fault handling isense1 isense2 isense3 isense1 isense2 fig. 2 : xrp 7713 block diagram
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 6 / 29 rev. 1.1. 1 pin assignment 30 29 28 27 26 25 24 23 21 22 19 18 16 17 15 14 12 13 11 10 1 2 3 4 5 6 7 8 9 32 20 31 avdd dvdd gpio1 gpio2 gpio3 gpio4 gpio5 enable gl2 lx2 gh2 bst2 vccd agnd vout1 vout2 vout3 pgnd3 gl3 lx3 gh3 bst3 ldoout vin vcca pgnd1 gl1 lx1 gh1 bst1 pgnd2 dgnd exposed pad: agnd xrp7713 tqfn 5mm x 5mm fig. 3 : xrp 7713 pin assignment pin description name pin number description vin 3 0 power source for the internal linear regulators to generate vcca, vdd and the standby ldo (ldoout). place a decoupling capacitor close to the controller ic. also used in uvlo1 fault generation C if vin falls below the user programmed limit, all c hannels are shut down. the vcca 29 output of the internal 5v ldo. this voltage is internally used to power analog blocks. this pin should be bypassed with a minimum of 4.7uf to agnd vccd 18 gate drive input voltage. this is not an output voltage. this pin can be connected to vcca to provide power for the gate drive. vccd should be connected to vcca with the shortest possible trace and decouple with a minimum 1 f capacitor . alternatively, vccd could be connected to an external supply (not greater than 5v ). pgnd1 ? 3 28, 23,13 power ground. ground connection for the low side gate driver. connect at low side fet source. avdd 32 output of the internal 1.8v ldo. this pin should be bypassed with a minimum of 2.2 uf to dgnd dvdd 1 input for powering the internal digital logic. this pin should be connected to avdd. dgnd 8 digital grou nd. connect this pin to the ground plane at the exposed pad with a separate trace. agnd 9 analog grou nd. connect this pin to the ground plane at the exposed pad with a separate trace
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 7 / 29 rev. 1.1. 1 name pin number description gl1 - gl 3 27, 22, 14 output pin of the low side gate driver. connect directly to the respective gate of an external n - channel mosfet. gh1 - gh 3 25, 20, 16 output pin of the high side gate driver. connect directly to the respective gate of an external n - channel mosfet. lx1 - lx 3 26, 21, 15 lower supply rail for the high - side gate driver (ghx) . connect this pin to the switching node at the junction between the two external power mosfets and the inductor. these pins are also used to measure voltage drop across bottom mosfets in order to provide output current information to the control engine. bst1 - bst 3 24, 19, 17 high side driver supply pin (s) . connect bst to an external boost diode and a capacitor as shown in the front page diagram. the high side driver is connected between the bst pin and lx pin . gpio 1 - gpio3 2,3,4 these pins can be configured as inputs or outputs to implement custom flags, power good signals and enable/disable controls. a gpio pin can also be programmed as an input clock synchronizing ic to external clock. refer to the gpio pins section and the external clock synchronization section for more information. gpio4_sda, gpio 5_scl 5,6 i 2 c serial interface communication pins. these pin s can be re - progr ammed to perform gpio functions in applications when i 2 c bus is not used. vout1 ? 4 10, 11, 12 voltage sense. connect to the output of the corresponding power stage. ldoout 31 output of the s tandby ldo. it can be configured as a 5v or 3.3v output . this pin should b e bypassed with a minimum of 2.2 uf. enable 7 if enable is pulled high, the chip power s up (logic reset, registers configuration loaded, etc.). if pulled low for long er than 100us , the xrp 7713 is placed into shutdown. agnd exposed pad analog ground. connect to analog ground (as noted above for pin 11). ordering information part number junction temp range marking package packing quantity note 1 default i 2 c address xrp 7713 ilb - f - 40c 7 j 12 5c xrp 7713 ilb yyww x 32- pin t qfn bulk halogen free 0x00 xrp 7713 ilbtr - f - 40c 7 j 12 5c xrp 7713 ilb yyww x 32- pin t qfn 3 k/tape & reel halogen free 0x00 xrp 7713 evb xrp 7713 evaluation board yy = year C ww = work week C x = lot number
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 8 / 29 rev. 1.1. 1 typical performance characteristics all data taken at t j = t a = 25c, unless otherwise specified - schematic and bom from application information section of this datasheet. fig. 4: 12vin efficiency: single channel 300khz - channels not in use are disabled fet: si4944; inductor: 744314xxx 7x7x5mm fig. 4 : 12vin efficiency: single channel 300khz - channels not in use are disabled fet: fds8984; inductor: 744310200 7x7x3mm fig. 5 : 5vin efficiency: single channel 300khz - channels not in use are disabled fet: si4944; inductor: 744314xxx 7x7x5mm fig. 6 : 5vin efficiency: single channel 300khz - channels not in use are disabled fet: fds8984; inductor: 744314xxx 7x7x3mm fig. 7 : combined efficiency: 3v3 1v8 & 1v0 300 khz fet: fds8984; inductor: 744314xxx 7x7x3mm fig. 8 : 12vin efficiency: single cha nnel 1mhz - channels not in use are disabled fet: fds8984; inductor:744310200 7x7x3mm 50% 60% 70% 80% 90% 100% 0 1 2 3 4 5 efficiancy output current (amps) 2.5v 1.8v 1.2v 1.0v
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 9 / 29 rev. 1.1. 1 fig. 9 : shutdown current 5.1v to 25v fig. 10: shutdown current 4.8v to 5.1v fig. 11: ch1:1.0v ch2:5v ch3:1.8v simultaneous start - up configuration fig. 12: ch1:1.0v ch2:5v ch3:1.8v simultaneous soft - stop fig. 13: ch1:1.0v ch2:5v ch3:1.8v sequential start - up configuration fig. 14: ch1:1.0v ch2:5v ch3:1.8v sequential soft - stop configuration vout shutdown = 0.8v, 1a load 100 110 120 130 140 150 160 170 180 190 200 5 10 15 20 25 isd ( a) vin (v) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 4.7 4.8 4.8 4.9 4.9 5.0 5.0 5.1 5.1 5.2 isd ( a) vin (v)
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 10/ 29 rev. 1.1. 1 fig. 15: ch1:1.0v ch2:5v ch3:1.8v sequential soft - stop configuration vout shutdown = 0.8v, no load fig. 16: load transient response ch1: iout (1a/div) ch2:vout(3.3v) fig. 17 : temperature regulation 1.0 v out (1% vout window) fig. 18 : temperature regulation 1. 8 v out (1% vo window) fig. 19 : temperature and voltage regulation 1. 0 v out (1% vout window) fig 21: line/load regulation 1.8 v out ( 1% vout window)
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 11/ 29 rev. 1.1. 1 features and benefit s general dpwm benefits: ? eliminate temperature and time variations as sociated with passive components in: ? output set point ? feedback compensation ? frequency set point ? under voltage lock out ? input voltage measurement ? gate drive dead time ? tighter parameter tolerances including operating frequency set point ? easy configuration and re - configuration for different v out , iout, cout, and inductor selection by simply changing internal pid coefficients. no need to change external passives for a new output specification. ? higher integration: many external circuits can be handled by monitoring or modifying internal registers ? selectable dpwm frequency and controller clock frequency other benefits: ? a single voltage is needed for regulation [no external ldo required]. ? i 2 c interface allows: ? communication with a system controller or other power management devices for optimized system function ? access to modify or read internal registers that control or monitor: ? output current ? input and output voltage ? soft - start/soft - stop time ? power good ? part temperature ? enable/disable o utputs ? over current ? over voltage ? temperature faults ? adjusting fault limits and d isabling/enabling faults ? packet error checking (pec) on i 2 c communication ? 5 configurable gpio pins, ( 3 if i 2 c is in use). pins can be configured in several ways: ? fault reporting (including ocp, ovp, temperature, soft - start in progress, power good) ? allows a logic level interface with other non - digital ics or as logic inputs to other devices ? possible to configure as traditional enable pin for all 3 outputs ? 2 gpios can b e dedicate d to the i 2 c interface as required by the customers design ? frequency and synchronization capability ? selectable switching frequency between 300khz and 1.5mhz ? channel to channel phase relationship is a fixed 90 degrees ? main oscillator clock and dpw m clock can be synchronized to external sources ? master, slave and stand - alone configurations are possible ? internal mosfet drivers ? qhuqdo7gulyhuv ) for each channel ? built - in automatic dead - time adjustment ? 30ns rise and fall times ? powerarc hitect? design and configuration software: ? in its simplest form only vin, vout, and iout for each channel is required. ? the software calculates configuration register content based upon customer requirements. pid coefficients for correct loop response (fo r automatic or customized designs) can be generated and sent to the device. ? configurations can be saved and/or recalled ? gpios can be configured easily and intuitively ? synchronization configuration can be adjusted ? interface can be used for real - time debuggi ng and optimization ? customizing xrp 7713 with customer parameters ? once a configuration is finalized it can be sent to exar and can reside in pre - programmed parts that customers can order with an individual part number. ? allows parts to be used without i 2 c in terface system benefits: ? reliability is enhanced via communication with the system controller which can obtain real time data on an output voltage, input voltage and current. ? system proces sors can communicate with the xrp 7713 directly to obtain data or mak e adjustments to react to circuit conditions ? a system process or could also be configured to log and analyze operating history, perform diagnostics and if required, take the supply off - line after m aking other system adjustments. ? if customer field service is a possibility for your end product, parameter reporting and history would provide additional capabilities for troubleshooting or aid in future system upgrades.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 12/ 29 rev. 1.1. 1 functional descripti on and operation the xrp 7713 is a three output di gital pulse width modulation (dpwm) controller with integrated gate drivers for the use in synchronous buck switching regulators. each output voltage can be programmed from 0.9v to 5.1v without the need of an external voltage divider. the wide range of the programmable dpwm switching frequency (from 300khz to 1.5mhz) enables the user to optimize for efficiency or component sizes. the digital regulation loop requires no external passive components for network compensation. the loop performance does not need to be compromised due to component tolerance, aging, and operating condition. each digital controller provides a number of safety features, such as over - current protection (ocp) and over - voltage protection (ovp). the chip also provides over - temperature p rotection (otp) and under - voltage lock - out (uvlo) for two input voltage rails. the xrp 7713 also has up to 5 gpios and a standby linear regulator to provide standby power. an i 2 c bus interface is provided to program the ic as well as to communicate with the host for fault reporting and handling, power rail monitoring, channel enable and disable, standby ldo voltage reconfiguration, and standby ldo enable and disable. the xrp 7713 offers a complete solution for soft - start and soft - stop. the delay and ramp of each pwm regulator can be independently controlled. during soft - stop, the output voltage ramps down with a programmable slope until it reaches a pre - set value. this pre - set val ue can be programmed between within zero volts and the target voltage with the same set target voltage resolution. r egister t ypes there are two types of registers in the xrp 7713 : read/write registers and read - only registers. the read/write registers are us ed for the control functions of the ic and can be programmed using configuration non - volatile memory (nvm) or through an i 2 c command. the read - only registers are for feedback functions such as error/warning flags and for reading the output voltage or curre nt. n on - v olatile c onfiguration m emory the non - volatile memory (nvm) in xrp 7713 stores the configuration data for the chip and all of the power rails. this memory is normally configured during manufacturing time. once a specific bit of the nvm is programmed , that bit can never be reprogrammed again [i.e. one - time programmable]. during chip power up, the contents in the nvm are automatically transferred to the internal registers of the chip. programmed cells have been verified to be permanent for at least 10 years and are highly reliable. p ower u p and s equencing r equirements the xrp 7713 can be programmed to sequence its outputs for nearly any imaginable loading requirement. however, there are some important sequencing requirements for the xrp 7713 itself. when power is applied to the xrp 7713 , the 5v vcca and 1.8v avdd regulators must come up and stabilize to provide power for the analog and digital blocks of the ic. the e nable pin must remain below its logic level high threshold until the a vdd is regulating to ensure proper loading of the configuration registers. for systems that control the e nable signal through a microcontroller or other processor, this is simply a matter of providing the proper delay to the e nable signal after power up. however, most users will want the part to automatically power up when power is applied to the system. to that end there are a number of recommended solutions. the most ideal sequencing method is to provide an rc time constant delay from dvdd to the e nable pin. a 10 kohm res istor and a 0.1uf are all that is required. if the system needs to externally control the e nable pin as well, it is recommended that the e nable pin be pulled to ground using an open drain i/o. using 3.3v active logic would back feed dvdd and exceed the m aximum rated voltage of the pin.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 13/ 2 9 rev. 1.1. 1 for those using active 3.3v or 5v logic on the e nable pin an rc delay from vcca to the e nable pin may be used. when using an rc delay from vcca, attention must be paid to the amount of bypass capacitance loading avdd sinc e it will delay the time it takes for avdd to power up and regulate. the avdd and dvdd pins do not require more than 2.2uf for proper bypassing. see figure 21 for the recommended components for sequencing the e nable pin through an rc delay from vcca. if more capacitance is added to avdd and dvdd, the time constant must be increased. once e nable is asserted, an internal chip_ready flag goes high and enables the i 2 c to acknowledge the hosts serial commands. channels that are configured as always - on channe ls are enabled. channels that are configured to be enabled by gpios are also enabled if the respective gpio is asserted. enable pin vcca 10k .1uf fig. 20 2 : rc delay for enable taken from vcca in almost all cases, a simple check will ensure proper sequencing has been achieved . vcca regulate s a t approximately 4.6v when the enable pin is logic level low and at 5.1v when e nable is asserted. vcca will typically power up and regulate before avdd and because the internal logic is not y et powered up there is no internal shutdown signal, it will regulate at 5.1v. once avdd has reached sufficient voltage (and e nable is low) it will assert the internal shutdown signal and vcca will reduce its regulated voltage to 4.6v. when the e nable is asserted, the chip will power up and vcca will regulate at 5.1v. if our device is sequenced properly, vcca will achieve 5.1v then drop down to 4.6v and toggle back to 5.1v. see figure 22 for an example. fig. 21 3 : vcca (green) startup waveform
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 14/ 29 rev. 1.1. 1 another power - up timing concern can be observed with slowly increasing input voltages. if the uvlo fault threshold is set to a value h igher than the value of vin when avdd has stabilized and the enable is asserted; the uvlo fault could as sert prior to vin reaching its final value. i ncreasing the value of the resistor in the rc delay will slow down the enable signal and prevent a premature uvlo fault. s tandby l ow d rop - out r egulator this 100ma low drop - out regulator can be programmed as 3.3v or 5v in set_stbldo_en_config r egister. its output is seen on the ldoout pin. this ldo is fully controllable via the enable pin (configured to turn on as soon as power is applied), a gpio, and/or i 2 c communication. the 5v output setting of the regulator i s only available if vin is above 6. 3 v, and the 3.3v output setting is available for the entire vin range from 4.75 to 25v. the standby ldo should be bypassed with a minimum of 2.2 uf ceramic capacitor. e nabling , d isabling and r eset the xrp 7713 is enabled v ia raising the enable pin high. the chip can then be disabled by lowering the same enable pin. there is also the capability for resetting the chip via an i 2 c softreset command. for enabling a specific channel, there are several ways that this can be achi eved. the chip can be configured to enable a channel at start - up as the default configuration residing in the non - volatile configuration memory of the ic. the channels can also be enabled using gpio pins and/or an i 2 c bus serial command. the registers tha t control the channel enable functions are the set_en_config and set_ch_en_i 2 c. i nternal g ate d rivers the xrp 7713 integrates internal gate drivers for all 4 pwm channels. these drivers are optimized to drive both high - side and low side n - mosfets for synchronous operation s . both high side and low side drivers h ave the capability of driving 1 nf load with 30ns rise and fall time. the drivers have built - in non - overlapping circuitry to prevent simultaneous conduction of the two mosfets. the built - in non - overlapping feature is disabled when the programmable dead time is selected. p rogrammable d ead t ime the programmable dead time feature provides customers the flexibility to optimize the system performance over pwm switching frequency, efficiency and component selections. there are three registers to control the dead time. the programmable dead time feature is enabled in the set_control_bit_reg register. if disabled, the built - in dead time control inside the driver will take over. the dead time between the turn off of the low side mosfet and the turn on of high side mosfet is controlled by the set_dt_rise_chx. on the other ha nd, the dead time between the turn off of high side mosfet and the turn on of the low side mosfet is controlled by set_dt_fall_chx. the actual lsb of the registers is variable depending on the switching frequency. ???? ???? ( ??? ) = 1 ???? 256
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 15/ 29 rev. 1.1. 1 f ault h andling while the chip is operating there are four different types of fault handling: ? under voltage lockout (uvlo) monitors the input voltage to the chip, and the chip will shutdown all channels if the voltage drops to critical levels. ? over temperat ure protection (otp) monitors the temperature of the chip, and the chip will shutdown all channels if the temperature rises to critical levels. ? over voltage protection (ovp) monitors the voltage of channel and will shutdown the channel if it surpasses its voltage threshold. ? over current protection (ocp) monitors the current of a channel, and will shutdown the channel if it surpasses its current threshold. the channel will be automatically restarted after a 200ms delay. under voltage lockout (uvlo) t he under voltage can be sensed on vin . the set_uvlo_warn_vinx register that sets the under voltage warning set point condition at 100mv increments. when the warning threshold is reached, the host is informed via a gpio or by reading the read_warn_flag registe r. the set_uvlo_targ_vin 1 register that controls the under voltage fault set point condition at 100mv increments. this fault condition will be indicated in the read_fault_warn register. when an under voltage fault condition occurs , the fault flag register is set and all of the xrp 7713 outputs are shut down. the measured input voltages can be read back using the read_vin1 register, and both registers have a resolution of 100mv per lsb. when the uvlo condition clears (voltage rises above the uvlo warning th reshold), the chip can be configured to automatically restart. vin this is a multi - function pin that provides power to both the s tandby linear regulator and internal linear regulators to generate v cca, vdd, and the standby ldo (ldout). it is also used as a uvlo detect ion pin. if vin falls below its user programmed limit, all channels are shut down. temperature monitoring and over temperature protection (otp) ? r eading the junction temperature this register allows the user to read back the temperature of the ic. the temperature is expressed in kelvin with a maximum range of 520k , a minimum of 200k , and an lsb of 5 degrees k . the temperature can be accessed by reading the read_ v t j register. ? over temperature warning there are also warning and fault flags that ge t set in the read_ovv_uvlo_ovt_flag register. the warning threshold is configurable to 5 or 10 degrees c below the fault threshold . when the junction temperature reaches 5 or 10 degrees c below the user defined set point , the over - temperature warning bit [ ot p w ] gets set in the read_ovv_uvlo_ovt_flag register to warn the user that the ic might go into an over temperature condition (and shutdown all of the regulators) . ? over temperature fault if the over temperature condition occurs both the otp and ot p w bits will be set in the read_ovv_uvlo_ovt_flag register and the ic will shut down all channels (but i 2 c will remain operational) . the actual over temperature threshold can be set by the user by using a 7bit set_thermal_shdn register with an lsb of 5k.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 16/ 29 rev. 1.1. 1 if the over temperature fault condition clears, then the ic can be set to restart the chip automatically. the restart temperature threshold can be set by the set_thermal_restart register. o utput v oltage s etting and m onitoring the output v oltage setting is con trolled by the set_ vout _target_chx register. this register allows the user to set the output voltage with a resolution of 50mv for output voltages between 0 and 2.5v and with a resolution of 100mv for output voltages between 2.6v and 5.1v. o utput voltage s higher than 5.1v can be achieved by adding an external voltage divider network. the output voltage of a particular channel can be read back using the read_ vout x register. output voltage from 0.9v to 5.1v per the equation below , for values between 0.9v and 5.1v the output voltage is equal to the binary number stored in the set_ vout _target_chx register multiplied by 50mv. when programming an output voltage from 2.6v to 5.1v, odd binary values should be avoided . as a result, the set resolution for an output vo ltage higher than 2.5v is 100mv. ? ??? = ??? _ ???? _ ?????? _ ??? 50 ?? output vout higher than 5.1v to set the output voltage higher than 5.1v, the user needs to add an external voltage divider. the resistors used in the voltage divider should be below 10 k . the set_ vout _target_chx register should be set to 0x32 which is equivalent to an output voltage of 2.5v without the external divider network. the output voltage regulation in this case might exceed 2% due to extra error from the resis tor divider. r 1 and r 2 follo ws the definition below . voutx pin vout5.1v r1 r2 fig. 22 4 : external divider network for high output voltage ? ??? = ? ? 1 ? 2 + 1? ??? _ ???? _ ?????? _ ??? 50 ?? output voltage lower than 0.9v the xrp 7713 can be programmed to regulate an output voltage lower than 0.9v . however, in this case the specification of 2 0mv output voltage accuracy is not guaranteed . o ver - v oltage p rotection (ovp) the o ver - v oltage p rotection (ovp) set_ovvp_register sets the over - voltage condition in predefined steps per channel . the over - voltage protection is always active even during soft - start condition. when the over - voltage condition is tripped , the controller will shut down th e channel. when the channel is shut down the controller will then set corresponding ovp fault bits in the read_ovv_uvlo_ovt_flag register. the vout ovp threshold is 150mv to 300mv above nominal vout for a voltage target of 2.5v or less. for the voltage target of 2.6v to 5.1v, the vout ovp thresh old is 300mv to 600mv.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 17/ 29 rev. 1.1. 1 once th e over - voltage channel is disabled, the controller will check the set_fault_resp_config_lb and set_fault_resp_config_hb to determine wh ether there are any following channels that need to be shut down. any following channel w ill be disabled when the channel with the over voltage fault is disabled. the channel(s) will remain disabled, until the host takes action to enable the channel(s). any of the fault and warning conditions can also be configured to be represented using the general purpose input output pins (gpio) to use as an interface with non i 2 c compatible devices. for further information on this topic see the gpio p ins section . during ovp fault shutdown of the channel, the customer has the option to choose two types of shutdown for each channel. the first shutdown is passive shutdown where the ic merely stops outputting pulses. the second shutdown is a brute force shutdown where the gl remains on as the channel reaches its discharged voltage. note that if the brut e force method is chosen, then gl will permanently remain high until the channel is re - enabled. o utput c urrent s etting and m onitoring xrp 7713 utilizes a low side mosfet rdson current sensing technique. the voltage drop on rdson is measured by dedicated current adc. the adc results are compared to a maximum current threshold and an over - current warning threshold to generate the fault and warning flags. maximum output current the maximum output current is set by the set_ v iout_max_ chx register and set_isense_param_chx register . the set_ v iout_max_chx register is a n 8 bit register. bit s [ 5:0 ] set the maximum current threshold and bits [ 7:6 ] set the o ver - current warning threshold. the lsb for the current limit register is 5 mv and the allowed voltage range is between 0 and 3 15 mv. to calculate t he maximum current limit , the user needs to provide the mos fet rdson. the maximum current can be calculated as: ??????? = ?????? ????? ?? where kt is the temperature coefficient of the mosfet rdson; vsense is the voltage across rdson; ioutmax is the maximum output current. over - c urrent warning the xrp 7713 also offers an over - current warning flag. this warning flag resides in the read_ovc_flag register. the warning flag bit will be set when the output current gets to within a specified value of the output current limit threshold enabling the host to reduce power consumption. the set_viout_max_chx register allows the warning flag threshold to be set 10mv, 20mv, 30mv or 40mv below viout_max. the warning flag will be automatically clear ed when the current drops below the warning threshold . over - c urrent fault ha ndling when an over - current condition occurs, pwm drivers in the corresponding channels a re disabled. after a 200ms timeout , the controller is re - powered and soft - start is initiated. w hen the over - current condition is reached the controller will check the set_fault_resp_config_lb and set_fault_resp_config_hb to determine wh ether there are any following channels that need to be similarly restarted. the controller will also s et the fault flags in read_ ovc_f ault_warn register.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 18/ 29 rev. 1.1. 1 typically the over - current fau lt threshold would be set to 130 - 140% of the maximum desirable output current. this will help avoid any over - current conditions caused by transients that would shut down the output channel. chip operation and configuration s oft - s tart the set_ss_rise_chx re gister is a 16 bit register which specifies the soft - start delay and the ramp characteristics for a specific channel . th is register allows the customer to program the channel with a 250 s step resolution and up to a maximum 16ms delay. bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit represents 250 s steps. bits [9:0] specify the rise time of the channel; these 10 bits define the number of microseconds for each 50mv increment to reach the target voltage . enable signal vout ss_rise _chx register bit [0:9] rise time delay bit [10:15 ] fig. 23 5 : channel po wer up sequence
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 19/ 29 rev. 1.1. 1 s oft - s top the set_pd_fall_chx register is a 16 bit register. this register specifies the soft - stop delay and ramp (fall - time) characteristics for when the chip receiv es a channel disable indication from the host to shutdown the channel. bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the channel; where each bit represents 250 s steps. bits [9:0] specify the fall time of the channel; these 10 bits define the number of microseconds for each 50mv increment to reach the discharge threshold . delay fall time bit [10:15] bit [0:9] vout enable signal pd_delay_chx register fig. 24 6 : channel soft - stop sequence p ower g ood f lag the xrp 7713 allows the user to set the upper and lower bound for a power good signa l per channel. the set_pwrg_targ_max_chx register sets the upper bound , the set_pwrg_targ_min_chx register sets the lower bound. each register has a 20mv lsb resolution . when the outpu t voltage is within bounds the power good signal is asserted high. typically the upper bound should be lower than the over - voltage threshold . in addition, the power good signal can be delayed by a programmable amount set in t he set_pwrgd_dly_chx register. t he power good delay is only set after the soft - start period is finished. if the channel has a pre - charged condition that falls into the power good region, a power good flag is not set until the soft - start is finished. pwm s witching f requency the pwm switc hing frequency is set by choosing the corresponding oscillator frequency and clock divider ratio in the set_sw_frequency register. bit s [ 6:4 ] set the oscillator frequency and bit s [2:0] set the clock divider. the tables below summarize the available main o scillator and pwm switching frequenc y settings in the xrp 7713 . main oscillator frequency set_sw_frequency[6:4] 000 001 010 011 100 101 110 111 main oscillator frequency 48mhz 44.8mhz 41.6mhz 38.4mhz 35.2mhz 32mhz 28.8mhz 25.6mhz ts 20.8ns 22.3ns 24ns 26ns 28.4ns 31.25ns 34.7ns 39ns
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 20/ 29 rev. 1.1. 1 pwm switching frequency set_sw_frequency[6:4] set_sw_frequency[2:0] 000 001 010 011 100 101 110 111 000 na na na na na na na na 001 1.5mhz 1.4mhz 1.3mhz 1.2mhz 1.1mhz 1.0mhz 900khz 800khz 010 1.0mhz 933khz 867khz 800khz 733khz 667khz 600khz 533khz 011 750khz 700khz 650khz 600khz 550khz 500khz 450khz 400khz 100 600khz 560khz 520khz 480khz 440khz 400khz 360khz 320khz 101 500khz 467khz 433khz 400khz 367khz 333khz 300khz na 110 429khz 400khz 370khz 343khz 314khz na na na 111 375khz 350khz 325khz 300khz na na na na there are a number of options that could result in similar pwm switching frequency as shown above. in general, the chip consumes less power at lower oscillator frequency. when synchronization of the main oscillator frequency to an external system clock is desired, the user must choose the oscillator frequency to be within 5% of the external clock frequency. a higher main oscillator frequency will not improve accuracy or any performance efficiency. note: it is the intention of the synchronization feature t o sync to a system clock or to another compatible exar device, not the switching frequency. pwm s witching f requency c onsideration s t here are several considerations when choosing the pwm switching frequency. minimum on time m inimum on time determine s the minimum duty cycle at the specific switching frequency . the minimum on time for the xrp 7713 is 40ns. ??????? ???? ????? % = ??????? ?????? ??? ????????? 100 as an example the minimum duty cycle is 4 % for 1mhz pwm frequency. this is important since the minimum on time dictates the maximum conversion ratio that the pwm controller can achieve . ??????? ???? ????? % > ???? ?????? maximum duty cycle the maximum duty cycle is dictated by the minimum required time to sample the current when the low side mosfet is on, this depends on the frequency of the main oscillator and the selected pwm frequency. it is best to choose the highest main oscillator frequency available for any specific pwm frequency. th e maximum duty cycle for each pwm frequency is shown in the table below: main oscillator frequency maximum duty cycle 48mhz 44.8mhz 41.6mhz 38.4mhz 35.2mhz 32mhz 28.8mhz 25.6mhz 78% 1.5mhz 1.4mhz 1.3mhz 1.2mhz 1.1mhz 1.0mhz 900khz 800khz 86% 1.0mhz 933khz 867khz 800khz 733khz 667khz 600khz 533khz 84% 750khz 700khz 650khz 600khz 550khz 500khz 450khz 400khz 89% 600khz 560khz 520khz 480khz 440khz 400khz 360khz 320khz 88% 500khz 467khz 433khz 400khz 367khz 333khz 300khz na 88% 429khz 400khz 370khz 343khz 314khz na na na 86% 375khz 350khz 325khz 300khz na na na na fig. 25 7 : pwm frequency
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 21/ 29 rev. 1.1. 1 t he maximum duty cycle obtained from the table above is programmed by the powerarchitect tm software into each of the channels using the set_duty_limiter_chx register. this ensures that under all conditions (including faults), there will always be sufficient sampling time to measure the output current. when the duty cycle limit is reached, the output voltage will no longer regulate and will be clamped based on the maximum duty cycle limit setting. it is possible for the user to program set_duty_limiter_chx register to a higher value, but the ocp fault and ocp warn flags should then be ignored. efficiency the pwm switching frequency plays an important role on overall power conversion efficiency. as the switching frequency increase, the switching losses also increase. please see the application information, typical performance data for further examples. component selection and frequency typical ly the components become smaller as the frequency increases, as long as the ripple requirements remain constant. at higher frequency the inductor can be smaller in value and have a smaller footprint while still maintaining the same current rating. f requenc y s ync hronization f unction and e xternal c lock the user of the xrp 7713 can choose to use an external source as the primary clock for the xrp 7713 . this function can be configured using the set_sync_mode_config register. this register sets the operation of th e xrp 7713 when an external clock is required. by selecting the appropriate bit combination the user can configure the ic to function as a master or a slave when two or more xrp 7713 s are used to convert power in a system. automatic clock selection is also provided to allow operation even if the external clock fails by switching the ic back to an in ternal clock. external clock synchronization even w hen configured to use an external clock , the chip initially powers up with its internal clock. the user can set the percent target that the frequency detector will use when comparing the internal clock with the clock frequency input on the gpio pin. if the external clock frequency is detected to be within th e window specified by the user, then a switchover will occur to the external clock. if the ic does not find a clock in the specified frequency target range then the external clock will not be used and the ic will run on the internal clock that was specified by the user. if the external clock fails the user can chose to have the internal clock take over , using the automatic switch back mode in the set_sync_mode_config register. xrp7713 configured for external clock use clk_in gpio1 fig. 26 8 : xrp 7713 configured fo r external clock use
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 22/ 29 rev. 1.1. 1 synchronized operation as a master and slave unit two xrp 7713 s can be synchronized together. this master - slave configuration is described below. ? master when the xrp 7713 powers up as a master unit after the internal configuration memor y is loaded the unit will sen d clk_out and sync_out signals to the slave on the preconfigured gpio pins . ? slave when powering in sync mode the slave unit will initially power up with its internal clock to transfer the configuration memory . once this transfe r occurs , then the unit is set to function as a slave unit. in turn the unit will take the external clock provided by the master to run as its main internal clock. gpio2 gpio2 xrp7713 configured as a master xrp7713 configured as a slave clk_out sync_out sync_in clk_in gpio1 gpio1 fig. 27 9 : master/slave configuration of t he xrp 7713 external c lock s ynchronization master slave combination when an external clock is used, the user will need to setup the master to also have an external clock in function. all of the same rules apply as in the external clock synchronization, synchronized operation as a slave unit section of this document. there are two ways of synchronizing this, either the external clock going to both master/slave clk_in, or clk_in can go to the master, and the master can synchronize sync_out and clk_out to the slave. gpio2 gpio2 xrp7713 configured as a master with external clock sync xrp7713 configured as slave sync_out sync_in clk_in clk_in gpio1 gpio1 fig. 30 28 : external clock synchronization master slave combination
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 23/ 29 rev. 1.1. 1 gpio2 gpio2 xrp7713 configured as a master with external clock sync xrp7713 configured as slave sync_out sync_in clk_in clk_in gpio1 gpio3 clk_out gpio1 fig. 29 1 : alternative external clock synchronization master slave combinatio n p hase s hift each switching channel is configured to run with a phase shift of 90 degrees. gpio p ins the general purpose input output (gpio) pins are the basic interface between the xrp 7713 and the system. although all of the stored data within the ic can be read back using the i2c bus it is sometimes convenient to have some of those internal register to be displayed and or controlled by a single data pin. besides simple input output functio ns the gpio pins can be configured to serve as external clock inputs. these pins can be programmed using otp bits or can be programmed using the i 2 c bus. this gpio_config register allows the user close to 100 different configuration functions that the gpio can be programmed to do. note: the gpio pins (and all i/os) should not be driven without a 10k resistor when vin is not being applied to the ic. gpio pins polarity the polarity of the gpio pin can be set by using the gpio_act_pol register. this register allo ws any gpio pin whether configured as an input or output to change polarity. bits [ 5:0 ] are used to set the polarity of gpio 1 though 5 . if the ic operates in i 2 c mode , then the commands for bits [5: 4 ] are ignored. supply rail enable each gpio can be c onfigured to enable a specific power rail for the system. the gpiox_cfg register allows a gpio to enable/disable any of the following rails controlled by the chip: ? a single buck power controller ? the standby ldo ? any mix of the standby ldo and power control ler(s) when the configured gpio is asserted externally, the corresponding rails will be enabled, and they will be similarly disabled when the gpio is de - asserted. this supply enabling/disabling can also be controlled through the i 2 c interface. power g ood i ndicator the gpio pins can be configured as power g ood indicators for one or more rails. the gpio pin is asserted when all rails configured for this specific io are within specified limits for regulation. this information can also be found in the read_p wrgd_ss_flag status register.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 24/ 29 rev. 1.1. 1 fault and warning indication the gpios can be configured to signal fault or warning conditions when they occur in the chip. each gpio can be configured to signal one of the following: ? ocp fault on channel 1 - 3 ? ocp warning on channel 1 - 3 ? ovp fault on channel 1 C 3 ? uvlo fault on vin ? uvlo warning on vin ? over temperature fault or warning i 2 c c ommunication the i 2 c communication is standard 2 - wire communication available between the host and the ic. the communicati on has the option of enabling packet error checking in order to deal with noisy environments where bit - errors could occur in the communication. this packet error checking is a crc - 8 code appended to all communication between the host and the ic. each xrp 7 713 in an i 2 c - bus system is activated by sending a valid address to the device. the address always has to be sent as the first byte after the start condition in the i 2 c - bus protocol msb 6 5 4 3 2 1 0 r/w lsb fig. 3 2 : alignment of i2c address in 8 bit byte there is one address byte required since 7 - bit addresses are used. the last bit of the address byte is the read/write - bit and should always be set according to the required operation. this 7 - bit i 2 c address is stored in the nvm. one can program a blan k device with the 7 - bit slave address or select one of the preprogrammed options. the 7 - bit address plus the r/w bit create an 8 - bit data value that is sent on the bus . the xrp 7713 ilb - 0x10 - f has an i 2 c address of 0x10. the internal registers are written by sending a data value of 0x20 and read by sending a data value of 0x21. this reflects the address being shifted one bit to the left and the least significant bit being set to reflect a read or write operation in order to stuff the byte correctly. the seco nd byte sent to the xrp 7713 is the location of a specific register. using gpio3 to select i 2 c address gpio3 may be used to change the lsb of the 7 - bit address. this option can be enabled within the powerarchitect tm software by checking the use gpio3 to control lsb of i2c address box at the top right of the digital design tab. more about the use of this option and other methods of changing the default i2c address of the part are available in anp - 31 power xr configuration and programming .
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 25/ 29 rev. 1.1. 1 e xternal c omponent s election inductor selection select the inductor for inductance l and saturation current isat. select an inductor with isat higher than the programmed over current limit. calculate inductance from: ? = ( ??? ? ???? ) ???? ??? 1 ?? 1 ???? where: vin is the converter input voltage vout is the converter output voltage fs is the switching frequency irip is the inductor peak - to - peak current ripple (nominally set to 30% of iout) keep in mind that a higher irip results in a smaller inductance value which has the advantages of smaller size, lower dc equivalent resistance (dcr), and allows the use of a lower output capacitance to meet a given step load transient. a higher irip, however, increases the output voltag e ripple, requires higher saturation current limit, and increases critical conduction. notice that this critical conduction current is half of irip. capacitor selection x output capacitor selection select the output capacitor for voltage rating, capacitance and equivalent series resistance (esr). nominally the voltage rating is selected to be at least twice as large as the output voltage. select the capacitance to satisfy the specification for output voltage overshoot/undershoot caused by the current step loa d. a sudden decrease in the load current forces the energy surplus in the inductor to be absorbed by cout. this causes an overshoot in output voltage that is corrected by power switch reduced duty cycle. use the follow ing equation to calculate cout: ? = ? ( ? 2 ? ? 1 ) 2 ? ?? 2 ? ? ??? 2 where: l is the output inductance i2 is the step load high current i1 is the step load low current vos is output voltage including the overshoot vout is the steady state output voltage or it can be expressed approximately by ? = ? ( ? 2 ? ? 1 ) 2 2 ???? ? ? ? here, out os v v v is the overshoot voltage deviation.
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 26/ 29 rev. 1.1. 1 select esr such that output voltage ripple ( vrip ) specification is met. there are two components in vrip . first component arises from the charge transferred to and from cout during each cycle. the second component of vrip is due to the inductor ripple current flowing through the output capacitors esr. it can be calculated for vrip: ???? = ???? ? ??? 2 + ? 1 8 ???? ?? ? 2 where: irip is the inductor ripple current fs is the switching frequency cout is the output capacitance note that a smaller inductor results in a higher irip, therefore requiring a larger cout and/or lower esr in order to meet vrip. with the current generation of ultra - low esr ceramic capacitors it is common to operate with irip ri,rxw when trying to optimize control loop bandwidth, particularly at switching frequencies below 600khz, an effective esr in the range of 7 to 20mo hm can help significantly. the digital power studio design tool is used to verify what will work best in your application. x input capacitor selection select the input capacitor for voltage, capacitance, ripple current, esr and esl. voltage rating is nomina lly selected to be at least twice the input voltage. the rms value of input capacitor current, assuming a low inductor ripple current, can be approximated as: ??? = ???? ? ? ( 1 ? ? ) where: iin is the rms input current iout is the dc output current d is th e duty cycle in general, the total input voltage ripple should be kept below 1.5% of vin . the input voltage ripple also has two major components: the voltage drop on the main capacitor cin v and the voltage drop due to esr - esr v . the contribution to input voltage ripple by each term can be calculated from: 2 ) ( in in s out in out out cin v c f v v v i v ) 5 . 0 ( rip out esr i i esr v total input voltage ripple is the sum of the above: esr cin tot v v v
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 27/ 29 rev. 1.1. 1 power mosfets selection selecting mosfets with lower rdson reduces conduction losses at the expense of increased switching losses. conduction losses are expressed by the two following equations. high side mosfet conducted loss: in out dson out cond v v r i p ? ? = 2 low side mosfet conducted loss: ? ? ? ? ? ? ? ? ? ? ? = in out dson out cond v v r i p 1 2 the mosfets junction temperature can be estimated from: ambient thja cond j t r p t + = 2 this assumes that the switching loss is the same as the conduction loss. thja r is the total mosfet thermal resistance from junction to ambient. l ayout g uidelines refer to application note anp - 32 practical layout guidelines for power xr designs .
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 28/ 29 rev. 1.1. 1 package specificatio n 32 - pin 5mmx5 mm tqfn
x x r r p p 7 7 7 7 1 1 3 3 t t h h r r e e e e c c h h a a n n n n e e l l d d i i g g i i t t a a l l p p w w m m s s t t e e p p d d o o w w n n c c o o n n t t r r o o l l l l e e r r ? 2010 exar corporation 29/ 29 rev. 1.1. 1 revision history revi sion date description 1.0.0 february 2010 initial release 1.0.3 march 2010 updated diagrams 1.1. 0 09/30/2010 added references to powerarchitect?. revised ja , revised i 2 c communication section. added power - up and sequencing requirements. changed schematics to include en pin sequencing. corrected conditions for ldo output voltage at 5v. added en pin threshold specification. changed input voltage operating range. added gpio3 i 2 c address selection. other minor modifications to wording. added esd rating. added negative lx transient specification. 1.1.1 12/07/2010 package drawing updated in revision 1.1.0 for legibility was incorrect . in particular, d2 and e2 . this has been corrected for further assistan ce email: customersupport@exar.com exar technical documentation: http://www.exar.com/techdoc/default.aspx? e xar c orporation h eadquarters and s ales o ffices 48720 kato road fremont, ca 94538 C usa tel.: +1 (510) 668 - 7000 fax: +1 (510) 668 - 7030 www.exar.com notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corpo ration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are onl y for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however , is assumed for inaccuracies. exar corporation does not recommend the us e of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequa tely protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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